In the field of display technology, oxide thin film transistors (TFTs) become a hot topic due to their higher carrier mobility, higher thermal and chemical stability with respect to amorphous-silicon thin film transistors (a-Si TFTs), wherein the carrier mobility of the oxide TFTs is ten times as great as that of the a-Si TFTs. The display device driven by the oxide TFT can meet the requirements of large size and high resolution display devices, especially meet the requirements of the next generation of active matrix organic light emitting devices (AMOLEDs), thus it dominates the field of flat panel display.
Currently, since the requirements for fabricating an oxide TFT are high, simplifying the device structure and process is a goal that people have been pursuing all the time under the premise of ensuring fabricating a high performance oxide TFT. The conventional oxide TFT usually uses a top gate type. FIG. 1 shows a conventional pixel electrode drive structure using a top gate type oxide TFT comprising: a substrate 101, an active layer 102 formed on the substrate 101, a gate insulating layer 103 formed on the active layer 102, a gate 104 formed on the gate insulating layer 103, an etch-stop layer 105 formed over the gate 104, a source and drain layer 106 (comprising a source and a drain) formed over the etch-stop layer 105, a passive layer 107 formed over the source and drain layer 106 and a pixel electrode 108 formed over the passive layer 107 and connected with the drain of the source and drain layer 106.
The top gate TFT as shown in FIG. 1 is fabricated by using the following 6-Mask process. A pattern process generally at least comprises a mask process, an exposure process, a development process, a lithography process and an etching process, wherein each exposure process uses a mask corresponding to pattern to be formed.
First, a pattern of an active layer 102 is formed through a first pattern process.
Second, patterns of a gate insulating layer 103 and the gate 104 are formed through a second pattern process. In the procedure, the gate 104 is firstly formed through a wet etching process, and then the gate insulating layer 103 is formed through a dry etching process.
Third, a pattern of an etch-stop layer 105 is formed through a third pattern process.
Fourth, a pattern of a source and drain layer 106 is formed through a fourth pattern process.
Fifth, a pattern of a passive layer 107 is formed through a fifth pattern process, wherein a contact hole is formed on the passive layer 107 configured to connect the drain electrode and the subsequently formed pixel electrode 108.
Six, a pattern of the pixel electrode 108 is formed through a six pattern process.
Accordingly, the conventional TFT has complex structure, and since 6-mask process is used to fabricate the high performance oxide, the process is complicated. Furthermore, since each additional pattern process may contaminate the function film layers of the oxide TFT, this method reduces the performance of the oxide TFT.